Semiconductor packages may comprise a carrier and a semiconductor chip attached to the carrier. The semiconductor chip and the carrier may exhibit different coefficients of thermal expansion (CTEs) which may induce stress in the semiconductor package, for example during the fabrication process of the semiconductor package or during operation. In the worst case the stress may even lead to delamination of components and to device failure. Furthermore, certain applications, for example optoelectronic applications, may require structuring the carrier in order to provide an optical passage to the semiconductor chip.